This invention relates to a method of laminating a polycrystalline silicon as a lining for forming functional elements such as diodes and transistors or an integrated circuit on the back surface of a single crystal (i.e., monocrystalline semiconductor wafer and dividing the wafer to form chips. The mechanical strength of the wafer is increased and the electric insulation is improved.
Heretofore, a chemical vapor deposition (CVD) method for depositing gaseous silicon on a semiconductor wafer by a thermal decomposition has been employed as a method of laminating a polycrystalline silicon of this type.
According to this method, the growing rate of the accumulated film (a CVD film) is very slow such as several hundred to several thousand angstroms per minute at a substrate temperature of 500.degree. to 600.degree. C. or higher, and the accumulated film thickness of the product obtained for practical use is only as high as 30 to 50 micron from the viewpoints of economy and mass productivity.
Recently, the thickness of a polycrystalline silicon layer is required to be at least 100 micron for protection against alpha-rays in semiconductor functional element to be used in space, but the problem of slow film growing rate cannot suitably meet the demand.
Since the CVD device also has a limit in its size, in case of a semiconductor wafer having a large diameter such as 5 to 8 inches, the conventional CVD device has such disadvantage that the number of wafers to be treated simultaneously is reduced, thereby extremely deteriorating the production efficiency.